Open Position

High-Speed Hardware Design Engineer – Architect & Lead position

Your responsibilities include:

  • Lead Architecture design and development
  • Design and document high-level and low-level diagrams of the system’s hardware/firmware requirements
  • Component selection and maintaining vendor relationships
  • Schematic capture and review
  • Manage PCB layout with our team of designers
  • Validation planning and execution
  • Custom silicon specifications and validation, from simple glue logic to multi-core ARM SoC’s
  • You will collaborate with cross functional teams involved in design and development process

Qualification and Key requirements:

  • Strong EE fundamentals and possess a deep understanding of why our discipline works the way it does; you’ve developed an intuition and can apply it to new topics because you understand the basics of electrical hardware
  • 8+ years of the following experience is preferred
  • Experience with High Speed Design concepts
  • Hands-on experience in prototype bring-up and debugging, as well as functional verification
  • Experience crafting high volume products from beginning to end and dealing with contract manufacturers is a huge plus
  • Aspire to be a lead, and lead technical initiatives in the team

Benefits:

  • Integration program in a professional, young & dynamic team
  • Professional development opportunities
  • Competitive salaries & benefits
  • Compensation package includes also additional health insurance, sport & social activities
  • International work environment

You can find out more about our benefits here.




Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.

Ivana Maričić
HR Manager


Apply for:
High-Speed Hardware Design Engineer – Architect & Lead position


    GRADUATION THESIS LIST

    #TopicDomain
    1Clock domain crossing – issues and how to overcome themDD
    2Scheduling techniques and their implementation for queue servicingDD
    3Functional safety approaches implementation  in digital designDD
    4Temperature sensor IP – Analysis, modeling and verificationAMS
    5Bandgap reference IP – Analysis, modeling and verificationAMS
    6Voltage regulator IP – Analysis, modeling and verificationAMS
    7Internal oscillator IP – Analysis, modeling and verificationAMS
    8Power-on Reset IP – Analysis, modeling and verificationAMS
    9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
    10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
    11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
    12SoC integration – 3PIAS ProjekatDD+DV
    13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
    14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
    15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
    16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
    17VIP Development – PCI ExpressDV
    18VIP Development – DDRDV
    19VIP Development – EthernetDV
    20VIP Development – USBDV
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    22VIP Development – DSIDV
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    25VIP Development – SLIMbusDV
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    Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.