Segment Controller Board 1/2

The goal of this project was to develop the Control board and perform the HW Verification.

Project Scope

The goal of this project was to:

  • Develop the Control board with:
    • Sitara AM6548 SoC with 4xARM®Cortex®-A53 (up to 1,1 GHz) and 2xARM®Cortex®-R5F (up to 400MHz) microprocessor subsystem (BGA784 pin)
    • LPDDR memory @1.33 GTps (FBGA200)
    • PCIe Gen2
    • 4xIEEE802.3 100BASE-TX SERCOS Ports
  • Perform the HW Verification with
    • Full requirements traceability
    • Full test automation
    • Fully automated test report generation
    • Integration with Jira

End product

  • 12-Layer PCB

Technologies and tools

  • Cadence Allegro for Schematic/Layout Design
  • Cadence Sigrity for Signal/Power Integrity
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GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.