With 14 years of experience in front-end digital design and nearly 20 engineers in two design centers, Elsys Eastern Europe is ready to satisfy a different application-specific IPs development.


Working closely with our customers, our engineers are able to seamlessly integrate into customer’s digital design teams or take full ownership of a digital design project. Our expertise covers:

  • ASIC front-end systems developing
  • FPGA systems developing
  • RTL, Power Aware, GLS simulations
  • Back-end flow on module level


Scope of work covered by our teams:

  • Project management and planning
  • Pre-synthesis tools setup, run
  • Functional spec assessment
  • Design specification, micro-architecture documents development
  • RTL code developing/reuse and maintenance
  • Test suite for debug
  • Regression runs
  • RTL Coverage analysis
  • Post-synthesis tools setup and run on module level


These projects enable us to gain valuable experience in verification of:

  • Automotive applications ICs
  • Multimedia application processors
  • Low power SoC
  • Multimedia subsystems
  • Different communication protocols
  • Memory controllers
  • FPGA programmable logic matrix
  • Debug and test logic


Products we have verified are developed for different industries:

  • Audio
  • Consumer Electronics / Multimedia
  • Health/Medical
  • Smart Grid
  • Automotive
  • Telecommunications
  • FPGA
  • High Performance Computing
Every ASIC/FPGA digital design project represents a challenge to reach a diverse set of goals. We are striving to provide fast and reusable but at the same time efficient and optimized architectural solutions that satisfy functional and performance requirements. On other side, we are managing dissipation and area goals using power and area saving architectural approaches.

Ivan Tolja-Arsić
Digital Design Domain Lead


1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.