We have more than 15 years of experience in all areas of IC layout with deep understanding of layout effects on analog design and IC production process. This allows us to provide high quality service to our customers around the globe and help them bring their IC products to the market.


Our main focus in IC layout is on optimal placement, matching, parasitics control and signal integrity, electromigration and design for manufacturability with high yield.

  •  Working with all major IDMs and foundries such as TSMC, GlobalFoundries – IBM, Xfab, TowerJazz – Panasonic, STM, TI, UMC, Dongbu, EM, NXP, AMS, Fujitsu, VIS.
  • Wide IC technology expertise in bulk CMOS, BCD and SOI technologies, process nodes from 500 nm down to 28 nm.
  • Experience with Deep Trench Isolation (DTI) technologies.
  • Strong experience in power application layout, RF layout, precision base-band layout and ultra low power layout.
  • Track record of on-time delivered high quality analog and mixed-signal IC layouts


Working on all levels of custom IC layout from parameterized (p-cell) and standard cells, IO and ESD cells to block level, module and top – chip level layout.

  • Layout planned and developed as IP or full ASIC design
  • Physical verification (DRC, LVS, ERC, antenna, density, EM, DFM…)
  • IC layout methodology implementation and development
  • Basic IC layout training courses
  • External analog and digital IP modules integration and physical verification on chip
  • Digital layout including floorplaning, P&R, physical verification, non-constrained


  • Ultra low power/leakage layout design (ULP) – 16 bit microcontroller
  • Wide variety of power management units (PMU) and modules
  • High power amplifiers with 3A sourcing capabilities and 300W in a chip – audio amplifier
  • Advanced high speed and high resolution ADCs – 15bits, 20MS/s SAR ADC
  • Performance critical and automotive circuits IC layout – Airbag monitoring, automotive communication interface
  • RF layout with frequencies up to 60GHz – Bluetooth and WiFi transceivers, automotive radar


  • Consumer electronics
  • Automotive
  • Audio
  • Medical
  • Communications / wireless

Zoran Dukić
HW System Design Domain lead


1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.