Advans group

Elsys Eastern Europe is a proud member of the ADVANS Group, which stands for an independent, highly specialized group of complementary engineering companies. The Advans group was founded in the millennium year of 2000 by Mr. Radomir Jovanovic, electrical engineer with a strong entrepreneurial spirit.


Led by a vision that only passion leads to excellence, Mr. Jovanovic has formed a group of companies that emphasize the importance of all stakeholders’ satisfaction. Consequently, the significant growth has been made and the group became one of the preferred service partners among the major industry players.


Care for the employees and strategic nurturing of their skills, career path and overall satisfaction were immediately recognized by the group’s clients as well as by potential employees. Nowadays, the Advans Group is proudly represented by more than eight hundred engineers on two continents, located in eleven design centers.



100 %




65 M



Advans Group is comprised of ELSYS Design, AVISTO and MECAGINE covering a wide range of expertise in electrical, software and mechanical engineering.


Moreover, ELSYS Design is specialized in embedded systems and ASIC design, with its subsidiaries ELSYS Eastern Europe and ELSYS America. AViSTO is specialized in software development, with its subsidiary Elsys Eastern Europe, while MECAGINE is focused on the mechanics of structure and systems.


In France, our design centers are in Paris, Rennes, Nantes, Grenoble, Lyon, Sophia Antipolis, Aix en Provence and Toulouse. In Serbia, they are in Belgrade and Novi Sad. In the United States, we are located in the Silicon Valley.


1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.