With 14 years of experience in verification and nearly 100 engineers in two design centers EEE has a long track of different verification projects – IP, subsystem and SoC level.


Working closely with many customers our engineers are fully able to integrate into customer’s verification teams, or take full ownership of a verification project. Our expertise covers:

  • Pure digital and digital-mixed-signal design verification
  • Simulation based verification using UVM/eRM/direct methodologies
  • RTL, Power Aware, GLS simulations
  • Formal Verification
  • Power analysis, Performance, Stress testing, CDC & RDC analysis
  • Firmware verification in simulation environment


Scope of work covered by our teams:

  • Project management and planning
  • Verification tools setup
  • Functional spec assessment
  • Verification Metrics, verification plan and test plans definition
  • Verification environment architecture definition, development and maintenance
  • Test suite development and debug
  • Regression runs
  • Coverage analysis


These projects enable us to gain valuable experience in verification of:

  • High-performance programmable SoC
  • Multimedia application processors
  • Low power SoC
  • Various ARM core based systems
  • Multimedia subsystems
  • Different communication protocols
  • Memory controllers
  • FPGA programmable logic matrix
  • Power, reset and clock management logic
  • Debug and test logic


Products we have been verified are developed for different industries:

  • Audio
  • Consumer Electronics / Multimedia
  • Health/Medical
  • Smart Grid
  • Automotive
  • Telecommunications
  • FPGA
  • High Performance Computing
There are no universal tools in IC design verification. Only a combination of different approaches, methodologies and tools will provide full verification coverage. But neither the best verification methodology nor the tools can replace the knowledge of engineers performing design verification. Read more...

Aleksandar Jakovljević
SoC DV Domain Lead


1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.