Supplier policy

Elsys Eastern Europe is committed to deliver high performance for its stakeholders, leading by example as ethical and responsible IT Company. For Elsys Eastern Europe, there is an inseparable connection between business success and corporate responsibility to its employees, business partners, society and the environment.

 

What Elsys Eastern Europe expects of suppliers:

  • Respect the protection of internationally proclaimed human rights
  • The elimination of all forms of forced and compulsory labor and child labor
  • The elimination of discrimination in respect of employment and occupation
  • Comply with all applicable trade and commercial laws

 

Our Supplier Performance Indicators and areas for potential improvements are as follows:

  • On time delivery
  • Quality of the service
  • Total cost improvement
  • Quality improvement
  • Environmental, health and safety improvements

 

All Elsys Eastern Europe suppliers and subcontractors that are involved in Elsys Eastern Europe high performance should have clear understanding of our expectations and activities as well as our commitments to ethical business practices and compliance with the law.

 

Regional Director

 

This Supplier policy was last updated February 2019.

EEE- Supplier policy R01 – Feb-19

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.