If you are a student, HW Design domain is an ideal place to start your ASIC/FPGA chips development run. You can build up your basic knowledge on digital design, VLSI design and microprocessor systems. Our training program will provide you with core education you need to take on a commercial project with highly-experienced engineers as your tutors. Read more about Digital design here.


For someone at the beginning of his career, this is the right field to start as you will acquire a broad knowledge base required to work in SoC verification. Being ready to learn, travel and integrate in a team of likeminded professionals is a must in such a demanding field. Luckily, at Elsys EE we provide full support for your development on this journey. Read more about Verification of digital design here.


This is the field where you can put your university-learned knowledge from analog electronics to practical use. AMS is an integral part of all the verification in mixed-signal chips, and it is one of the most sought-after fields today, as over 90% of all chips in production today are mixed-signal chips. You will collaborate directly with highly-experienced analog designers and enjoy the work in the field that is still in development. Read more about Mixed signal verification here.


Despite the advancements in digital technology, large number of electronic blocs will still remain in the analogue domain as well as the need for their physical design using the Custom IC Layout methodology. Young engineers will find that Elsys EE provides the right support and supervision from highly-experienced colleagues as they work on real projects within our company. Read more about IC layout here.


1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.