My Engineering Story: Igor, Senior Staff ASIC/FPGA Design Engineer

From high-power motor control to low-power SoC, combining analytical precision with creative problem-solving, the very essence of what drew me to engineering in the first place.

My interest in technology began at an early age, as I eagerly waited for electronic devices to malfunction, always hoping to see what was inside when someone tried to fix them. An especially memorable experience came when my father took away a small electric motor from a broken toy, connect it to the battery and it started spinning. From that moment on, I began combining it with  gears, wheels, ropes, toy cars, creating small machines performing interesting tasks.

During the high-school my love for music expanded my interest in electronics to solid state audio power amplifiers. That was a great journey of saving the money for electronic components, doing a home made PCBs with marker pen drawing and later etching, and the exiting moments of first starts, expecting the clean music while preparing for a MOSFET burnout. After the high-school, I enrolled at the Faculty of Electronic Engineering in Niš, where I began a new chapter and gained a deeper understanding of electronics. During this time, I developed a strong interest in digital electronics. Exploring the world of digital circuits like microprocessors, microcontrollers, FPGAs strengthened my path in the field, so after the studies I pursued PhD studies and I graduated with a PhD in field of Networks-on-Chip.

Today, as a Senior Staff ASIC/FPGA Design Engineer at ELSYS Eastern Europe, I tackle a wide range of challenges, from high-power motor control to low-power SoC, combining analytical precision with creative problem-solving, the very essence of what drew me to engineering in the first place. My work is a combination of creativity and precision, balancing optimal design complexity with ensuring proper circuit timing.

WHERE PASSION LEADS TO EXCELLENCE

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GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.