Open Position

Digital Design Verification Engineer (Mid / Senior / Technical Expert)

Technologies & Tools:

  • UVM, SystemVerilog, SVA
  • C/C++, SystemC (nice to have)
  • Synopsys VCS, Verdi
  • Git, SVN, Perforce, ClearCase
  • PCIe (strong plus)
  • Ethernet, RISC-V, DFT (nice to have)

We are looking for candidates who have:

  • Minimum of 3 years of experience in digital design verification, as well as experienced engineers interested in taking on a technical leadership role
  • Advanced debugging and problem-solving skills
  • Proactive mindset with the ability to drive technical improvements and best practices
  • Team-oriented, with the ability to collaborate in an international environment

Benefits:

  • Opportunity to work with an experienced engineering team on global projects
  • Professional growth through internal and external training programs
  • Private health insurance
  • Flexible working model (hybrid)
  • Supportive and dynamic work environment

You can find out more about our benefits here.

 

All interested candidates are invited to submit their CV in English by February 15.




Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.

Kristina Radivojević
Recruitment and HR Specialist

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Digital Design Verification Engineer (Mid / Senior / Technical Expert)



    GRADUATION THESIS LIST

    #TopicDomain
    1Clock domain crossing – issues and how to overcome themDD
    2Scheduling techniques and their implementation for queue servicingDD
    3Functional safety approaches implementation  in digital designDD
    4Temperature sensor IP – Analysis, modeling and verificationAMS
    5Bandgap reference IP – Analysis, modeling and verificationAMS
    6Voltage regulator IP – Analysis, modeling and verificationAMS
    7Internal oscillator IP – Analysis, modeling and verificationAMS
    8Power-on Reset IP – Analysis, modeling and verificationAMS
    9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
    10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
    11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
    12SoC integration – 3PIAS ProjekatDD+DV
    13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
    14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
    15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
    16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
    17VIP Development – PCI ExpressDV
    18VIP Development – DDRDV
    19VIP Development – EthernetDV
    20VIP Development – USBDV
    21VIP Development – CSIDV
    22VIP Development – DSIDV
    23VIP Development – UNIPRODV
    24VIP Development – I3CDV
    25VIP Development – SLIMbusDV
    26VIP Development – HDMIDV
    Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.