Analog Custom IC Layout Engineer
Key Responsibilities / Duties:
- Floorplan, integrate, estimate area and create abstract views
- Place and route on block, top and full chip level in Cadence environment
- Work on I/O and ESD blocks as well as PAD and seal ring
- Work on physical layout verification (DRC, LVS, ERC and other) and debug
- Perform parasitic and EM extractions and work closely with Design Engineers and other IC Layout Engineers
Qualification Requirements:
- As a successful candidate you should be industry degree qualified in Electrical Engineering, B.Sc., M.Sc. or equivalent
- Have 2+ years of Analog IC Layout experience preferably using Cadence Virtuoso, Assura, PVS or Mentor Calibre tools.
- Knowledge and experience with other CAD tools for custom IC layout is strong plus.
- You should have good knowledge about standard Analog IC layout methodologies, understanding of IC technology processes and IC manufacturing, ESD and LU effects, EM, DFM, antenna effects, LDE and other challenges in analog IC layout design in sub-micron technologies.
- Knowledge of Linux system, SKILL, Shell scripting, Perl, TCL will be beneficial to your application.
- Good knowledge of English language and communication skills are important for this position.
Benefits:
- Integration program in a professional, young & dynamic team
- Professional development opportunities
- Competitive salaries & benefits
- Compensation package includes also additional health insurance, sport & social activities
- International work environment
You can find out more about our benefits here.
