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Expertise
Digital Design
Verification of Digital Design
Analog Mixed-Signal Verification
IC layout
About Us
Elsys Offices
ISO certificates
Advans group
TECH+
TECH+fpga
TECH+ftn
Blog
Career
Open Positions
Internship
Scholarship
Open Day
Life at Elsys
GRADUATION THESIS LIST
#
Topic
Domain
1
Clock domain crossing – issues and how to overcome them
DD
2
Scheduling techniques and their implementation for queue servicing
DD
3
Functional safety approaches implementation in digital design
DD
4
Temperature sensor IP – Analysis, modeling and verification
AMS
5
Bandgap reference IP – Analysis, modeling and verification
AMS
6
Voltage regulator IP – Analysis, modeling and verification
AMS
7
Internal oscillator IP – Analysis, modeling and verification
AMS
8
Power-on Reset IP – Analysis, modeling and verification
AMS
9
IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDP
DV
10
IP verification – MAC merge sublayer IP – MMSL – MAC Rx
DV
11
IP verification – MAC merge sublayer IP – MMSL – MAC Tx
DV
12
SoC integration – 3PIAS Projekat
DD+DV
13
SoC integration – ARM – Cortex M0 platform Integration using ARM SDK
DD+DV
14
SoC integration – ARM – Cortex M3 platform Integration using ARM SDK
DD+DV
15
SoC Verification – interdisciplinary themes – SW coverage collection and analysis
DV
16
SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)
DV
17
VIP Development – PCI Express
DV
18
VIP Development – DDR
DV
19
VIP Development – Ethernet
DV
20
VIP Development – USB
DV
21
VIP Development – CSI
DV
22
VIP Development – DSI
DV
23
VIP Development – UNIPRO
DV
24
VIP Development – I3C
DV
25
VIP Development – SLIMbus
DV
26
VIP Development – HDMI
DV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.